1. Field of the Invention
The present invention relates an input receiver and an operation method thereof, and particularly to an input receiver and an operation method thereof that can have lower power consumption when the input receiver enters a power down mode, and have a good setup time, a good hold time, a shorter response time, and better noise immunity when the input receiver enters or leaves the power down mode.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating an input receiving circuit 102 for receiving an external clock enable signal XCKE and an enable register 104 according to the prior art. As shown in FIG. 1, when the external clock enable signal XCKE is changed from high to low, an internal clock enable signal ICKE outputted by the input receiving circuit 102 can be also immediately changed from high to low, and the enable register 104 can keep a latch clock enable signal LCKE outputted thereof low according to an inner clock ICLK, resulting in a system buffer (e.g. a clock buffer, an address buffer, a command buffer, or a data buffer of a dynamic random access memory) receiving the latch clock enable signal LCKE being turned off. That is to say, the system enters a power down mode.
In addition, when the external clock enable signal is changed from low to high, the internal clock enable signal ICKE outputted by the input receiving circuit 102 can be also immediately changed from low to high, and the enable register 104 can keep the latch clock enable signal LCKE outputted thereof high according to the inner clock ICLK, resulting in the system buffer (e.g. the clock buffer, the address buffer, the command buffer, or the data buffer of a dynamic random access memory) receiving the latch clock enable signal LCKE being turned on. That is to say, the system leaves the power down mode.
In the prior art, the input receiving circuit 102 has either larger power consumption, or worse noise immunity. Therefore, how to design a better input receiving circuit becomes an important issue for an integrated circuit designer.